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FUNCTIONAL INTERNAL BLOCK DESCRIPTION
INTRODUCTION
The Phase Error Flag is the triple OR of phase errors from
each phase. Each phase error is the OR of the high side and
low side phase errors. This flag can generate an interrupt if
the appropriate mask bit is set. The INT will be held in the
High state until the fault is removed, and the appropriate bit
in the Status Register 0 is cleared by the CLINT1 command.
This fault reporting mechanism is described in detail in the
Logic Commands and Registers section.
HOLD OFF CIRCUIT
The IC guarantees the output FETs are turned off in the
absence of V DD or V PWR by means of the Hold off circuit. A
small current source, generated from VBAT, typically 100 μA,
is mirrored and pulls all the output gate drive pins low when
V DD is less than about 3.0V, RST is active (low), or when VLS
is lower than the VLS_Disable threshold.
CHARGE PUMP
The Charge Pump circuit provides the basic switching
elements required to implement a charge pump when
combined with external capacitors and diodes for enhanced
low voltage operation.
When the 33927 is connected per the typical application
using the charge pump (see Figure 17 ), the regulation path
for VLS includes the charge pump and a linear regulator. The
regulation set point for the linear regulator is nominally at
15.34V. As long as VLS output voltage (VLS OUT ) is greater
than the VLS analog regulator threshold (VLS ATH ) minus
V THREG , the charge pump is not active.
If VLS OUT < VLS ATH – V THREG the charge pump turns ON
Figure 14. Short to Battery Detection
Phase Comparator
Faults could also be detected as Phase Errors . A phase
error is generated if the output signal (at Px_HS_S) does not
properly reflect the drive conditions.
A phase error is detected by a Phase Comparator. The
Phase Comparator compares the voltage at the Px_HS_S
node with a reference of one half the voltage at the VBAT pin.
A high side phase error (which will also trigger the
Desaturation Detector) occurs when the high side FET is
commanded on, and Px_HS_S is still low at the end of the
deadtime and blanking time duration. Similarly, a LS phase
error occurs when the low side FET is commanded on, and
the Px_HS_S is still high at the end of the deadtime and
blanking time duration.
until VLS OUT > VLS ATH – V THREG + V HYST
V HYST is approximately 200mV. VLS ATH will not interfere
with this cycle even when there is overlap in the thresholds
due to the design of the regulator system.
The maximum current the charge pump can supply is
dependent on the pump capacitor value and quality, the
pump frequency (nominally 130kHz) and the Rdson of the
pump FETs. The effective charge voltage for the pump
capacitor would be V BAT – 2*V DIODE . The total charge
transfer would then be C PUMP * (V BAT – 2*V DIODE ).
Multiplying by the switch frequency gives the theoretical
current the pump can transfer: F PUMP * C PUMP * (V BAT –
2*V DIODE ).
NOTE: There is also another smaller, fully integrated
charge pump (Trickle Charge Pump - see Figure 2 ), which is
used to maintain the high-side drivers’ gate V GS in 100
percent duty cycle modes.
33927
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
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